Method and apparatus for asynchronous processor with a token ring based parallel processor scheduler

ABSTRACT

A method of operating a clock-less asynchronous processing system comprising a plurality of successive asynchronous processing components. The method comprises providing a first token signal path in the plurality of processing components to allow propagation of a token through the processing components. Possession of the token by one of the processing components enables the processing component to conduct a transaction with a resource component that is shared among the processing components. The method comprises propagating the token from one processing component to another processing component along the token signal path.

CROSS REFERENCE TO RELATED APPLICATIONS

This application claims priority under 35 USC 119(e) to U.S. ProvisionalApplication Ser. Nos. 61/874,794, 61/874,810, 61/874,856, 61/874,914,61/874,880, 61/874,889, and 61/874,866, all filed on Sep. 6, 2013, andall of which are incorporated herein by reference.

This application is related to:

U.S. patent application Ser. No. ______ entitled “METHOD AND APPARATUSFOR ASYNCHRONOUS PROCESSOR WITH FAST AND SLOW MODE” and filed on thesame date herewith, and identified by attorney docket numberHUAW07-06583, and which is incorporated herein by reference;

U.S. patent application Ser. No. ______ entitled “METHOD AND APPARATUSFOR ASYNCHRONOUS PROCESSOR REMOVAL OF META-STABILITY” and filed on thesame date herewith, and identified by attorney docket numberHUAW07-06400, and which is incorporated herein by reference;

U.S. patent application Ser. No. ______ entitled “METHOD AND APPARATUSFOR ASYNCHRONOUS PROCESSOR WITH A TOKEN RING BASED PARALLEL PROCESSORSCHEDULER” and filed on the same date herewith, and identified byattorney docket number HUAW07-06376, and which is incorporated herein byreference;

U.S. patent application Ser. No. ______ entitled “METHOD AND APPARATUSFOR ASYNCHRONOUS PROCESSOR PIPELINE AND BYPASS PASSING” and filed on thesame date herewith, and identified by attorney docket numberHUAW07-06364, and which is incorporated herein by reference; and

U.S. patent application Ser. No. ______ entitled “METHOD AND APPARATUSFOR ASYNCHRONOUS PROCESSOR BASED ON CLOCK DELAY ADJUSTMENT” and filed onthe same date herewith, and identified by attorney docket numberHUAW07-06351, and which is incorporated herein by reference.

TECHNICAL FIELD

The present disclosure relates generally to asynchronous processors, andmore particularly to an asynchronous processor with a token ring basedparallel processor scheduler.

BACKGROUND

High performance synchronous digital processing systems utilizepipelining to increase parallel performance and throughput. Insynchronous systems, pipelining results in many partitioned orsubdivided smaller blocks or stages and a system clock is applied toregisters between the blocks/stages. The system clock initiates movementof the processing and data from one stage to the next, and theprocessing in each stage must be completed during one fixed clock cycle.When certain stages take less time than a clock cycle to completeprocessing, the next processing stages must wait—increasing processingdelays (which are additive).

In contrast, asynchronous systems (i.e., clockless) do not utilize asystem clock and each processing stage is intended, in general terms, tobegin its processing upon completion of processing in the prior stage.Several benefits or features are present with asynchronous processingsystems. Each processing stage can have a different processing delay,the input data can be processed upon arrival, and consume power only ondemand.

FIG. 1 illustrates a prior art Sutherland asynchronous micro-pipelinearchitecture 100. The Sutherland asynchronous micro-pipelinearchitecture is one form of asynchronous micro-pipeline architecturethat uses a handshaking protocol built by Muller-C elements to controlthe micro-pipeline building blocks. The architecture 100 includes aplurality of computing logic 102 linked in sequence via flip-flops orlatches 104 (e.g., registers). Control signals are passed between thecomputing blocks via Muller C-elements 106 and delayed via delay logic108. Further information describing this architecture 100 is publishedby Ivan Sutherland in Communications of the ACM Volume 32 Issue 6, June1989 pages 720-738, ACM New York, N.Y., USA, which is incorporatedherein by reference.

Now turning to FIG. 2, there is illustrated a typical section orprocessing stage of a synchronous system 200. The system 200 includesflip-flops or registers 202, 204 for clocking an output signal (data)206 from a logic block 210. On the right side of FIG. 2 there is shownan illustration of the concept of meta-stability. Set-up times and holdtimes must be considered to avoid meta-stability. In other words, thedata must be valid and held during the set-up time and the hold time,otherwise a set-up violation 212 or a hold violation 214 may occur. Ifeither of these violations occurs, the synchronous system maymalfunction. The concept of meta-stability also applies to asynchronoussystems. Therefore, it is important to design asynchronous systems toavoid meta-stability. In addition, like synchronous systems,asynchronous systems also need to address various potentialdata/instruction hazards, and should include a bypassing mechanism andpipeline interlock mechanism to detect and resolve hazards.

Accordingly, there are needed asynchronous processing systems,asynchronous processors, and methods of asynchronous processing that arestable and detect and resolve potential hazards.

SUMMARY

According to one embodiment, there is provided a method of operating aclock-less asynchronous processing system comprising a plurality ofsuccessive asynchronous processing components. The method comprisesproviding a first token signal path in the plurality of processingcomponents to allow propagation of a token through the processingcomponents. Possession of the token by one of the processing componentsenables the processing component to conduct a transaction with aresource component that is shared among the processing components. Themethod comprises propagating the token from one processing component toanother processing component along the token signal path.

In another embodiment, there is provided a clock-less asynchronousprocessing system. The processing system comprises a plurality ofsuccessive asynchronous processing components, each processing componentcomprising token processing logic configured to receive, hold and pass atoken from a given processing component to another processing component.The token processing logic comprises token signal path in the pluralityof processing components to allow propagation of the token through theprocessing components. Possession of the token by one of the processingcomponents enables the processing component to conduct a transaction aresource component that is shared among the processing components.

BRIEF DESCRIPTION OF THE DRAWINGS

For a more complete understanding of the present disclosure, and theadvantages thereof, reference is now made to the following descriptionstaken in conjunction with the accompanying drawings, wherein likenumbers designate like objects, and in which:

FIG. 1 illustrates a prior art asynchronous micro-pipeline architecture;

FIG. 2 is a block diagram illustrating the concept of meta-stability ina synchronous system;

FIG. 3A illustrates an asynchronous processing system in accordance withdisclosed embodiments of the present disclosure;

FIG. 4 illustrates an example of a token ring architecture in accordancewith disclosed embodiments of the present disclosure;

FIG. 5 illustrates an example of an asynchronous processor architecturein accordance with disclosed embodiments of the present disclosure;

FIG. 6 illustrates token based pipelining with gating within an ALU inaccordance with disclosed embodiments of the present disclosure;

FIG. 7 illustrates token based pipelining for an inter-ALU token passingsystem in accordance with disclosed embodiments of the presentdisclosure;

FIG. 8 illustrates a block diagram of an exemplary token ring basedarray architecture in accordance with disclosed embodiments of thepresent disclosure;

FIG. 9 illustrates an exemplary embodiment of a token ring basedparallel processor asynchronous scheduler in accordance with disclosedembodiments of the present disclosure;

FIG. 10 illustrates a more detailed view of the token ring basedparallel processor asynchronous scheduler of FIG. 9 in accordance withdisclosed embodiments of the present disclosure;

FIG. 11 illustrates an example communication system in which theasynchronous processor and processing system may be utilized; and

FIGS. 12A and 12B illustrate example devices in which the asynchronousprocessor and processing system may be utilized.

DETAILED DESCRIPTION

Asynchronous technology seeks to eliminate the need of synchronoustechnology for a global clock-tree which not only consumes an importantportion of the chip power and die area, but also reduces the speed(s) ofthe faster parts of the circuit to match the slower parts (i.e., thefinal clock-tree rate derives from the slowest part of a circuit). Toremove the clock-tree (or minimize the clock-tree), asynchronoustechnology requires special logic to realize a handshaking protocolbetween two consecutive clock-less processing circuits. Once aclock-less processing circuit finishes its operation and enters into astable state, a signal (e.g., a “Request” signal) is triggered andissued to its ensuing circuit. If the ensuing circuit is ready toreceive the data, the ensuing circuit sends a signal (e.g., an “ACK”signal) to the preceding circuit. Although the processing latencies ofthe two circuits are different and varying with time, the handshakingprotocol ensures the correctness of a circuit or a cascade of circuits.

Hennessy and Patterson coined the term “hazard” for situations in whichinstructions in a pipeline would produce wrong answers. A structuralhazard occurs when two instructions might attempt to use the sameresources at the same time. A data hazard occurs when an instruction,scheduled blindly, would attempt to use data before the data isavailable in the register file.

With reference to FIG. 3A, there is shown a block diagram of anasynchronous processing system 300 in accordance with the presentdisclosure. The system 300 includes an asynchronous scalar processor310, an asynchronous vector processor 330, a cache controller 320 andL1/L2 cache memory 340. As will be appreciated, the term “asynchronousprocessor” may refer to the processor 310, the processor 330, or theprocessors 310, 330 in combination. Though only one processor 310, 330is shown, the processing system 300 may include more than one of theseprocessors. In addition, it will be understood that each processor mayinclude therein multiple CPUs, control units, execution units and/orALUs, etc. For example, the asynchronous scalar processor 310 mayinclude multiple execution units with each execution unit having adesired number of pipeline stages. In one example, the processor 310 mayinclude sixteen execution units with each execution unit having fivestages. Similarly, the asynchronous vector processor 330 may includemultiple execution units with each execution unit having a desirednumber of pipeline stages.

The L1/L2 cache memory 340 may be subdivided into L1 and L2 cache, andmay also be subdivided into instruction cache and data cache. Likewise,the cache controller 320 may be functionally subdivided.

Aspects of the present disclosure provide architectures and techniquesfor a clock-less asynchronous processor architecture that utilizes atoken ring based parallel processor scheduler. A token system is atwo-dimensional system. Within a functional unit, tokens gate each otherto form a closed loop. Across functional units, a token signal isdelayed “deliberately” to avoid a structural hazard. A token-basedasynchronous processor uses a token system to “emulate” a pipeline toyield instruction-level-parallelism (ILP) to preserve the program order,and avoid the data/structural/control hazards.

FIG. 4 illustrates an example of a token ring architecture 600 as analternative to the architecture above in FIG. 1. The components of thisarchitecture are supported by standard function libraries for chipimplementation. For example, the token ring architecture 600 comprises atoken processing logic unit 610. The token processing logic 610comprises token-sense-latch-logic 612 and a variable delay chain 614. Insome embodiments, the token processing logic unit 610 may also comprisepulse/active generation logic 616. The token processing logic unit 610may include any suitable circuitry for detecting reception of a token.The token processing logic unit 610 is configured to propagate the tokenfrom one processing component to other processing components along atoken signal path.

As described above with respect to FIG. 1, the Sutherland asynchronousmicro pipeline architecture requires the handshaking protocol, which isrealized by the non-standard Muller-C elements. In order to avoid usingMuller-C elements (as in FIG. 1), a series of token processing logicunits are used to control the processing of different computing logic(not shown), such as processing units on a chip (e.g., ALUs) or otherfunctional calculation units, or the access of the computing logic tosystem resources, such as registers or memory. To cover the long latencyof some computing logic, the token processing logic unit 610 isreplicated to several copies and arranged in a series of tokenprocessing logic units as shown at 620. Each token processing logic unit610 in the series 620 controls the passing of one or more token signals630 (associated with one or more resources). A token signal 630 passingthrough the token processing logic units in series 620 forms a tokenring 640. The token ring 640 regulates the access of the computing logic(not shown) to the system resource (e.g., memory, register) associatedwith that token signal. The token processing logic 610 accepts, holds,and passes the token signal 630 between each other in a sequentialmanner. When the token signal 630 is held by the token processing logic610, the computing logic associated with that token processing logic isgranted the exclusive access to the resource corresponding to that tokensignal, until the token signal is passed to a next token processinglogic in the ring. Holding and passing the token signal concludes thecomputing logic's access or use of the corresponding resource, and isreferred to herein as consuming the token. Once the token is consumed,it is released by the given token processing logic unit to a subsequenttoken processing logic unit in the ring.

FIG. 5 illustrates an asynchronous processor architecture 3101. Thearchitecture includes a plurality of self-timed (asynchronous)arithmetic and logic units (ALUs) 3122 coupled in parallel in a tokenring architecture as described above with respect to FIG. 4. Each ALU3122 may correspond to the token processing logic unit 610 of FIG. 4.The asynchronous processor architecture 3101 also includes a feedbackengine 3120 for properly distributing incoming instructions between theALUs 3122, an instruction/timing history table 3115 accessible by thefeedback engine 3120 for determining the distribution of instructions, aregister (memory) 3102 accessible by the ALUs 3122, and a crossbar 3124for exchanging needed information between the ALUs 3122. The historytable 3115 is used for indicating timing and dependency informationbetween multiple input instructions to the processor system.Instructions from the instruction cache/memory are received by thefeedback engine 3120 which detects or calculates the data dependenciesand determines the timing for instructions using the history table 3115.The feedback engine 3120 pre-decodes each instruction to decide how manyinput operands this instruction requires. The feedback engine 3120 thenlooks up the history table 3115 to find whether this piece of data is onthe crossbar 3124 or on the register file 3102. If the data is found onthe crossbar 3124, the feedback engine 3120 calculates which ALUproduces the data. This information is tagged to the instructiondispatched to the ALUs 3122. The feedback engine 3120 also updates thehistory table 3115 accordingly. A more detailed explanation of theasynchronous architecture 3101 is provided in co-pending applicationentitled “Method and Apparatus for Asynchronous Processor Pipeline andBypass Passing”, attorney docket number HUAW07-06364, filed concurrentlyherewith and incorporated herein by reference.

FIG. 6 illustrates token based pipelining with gating within an ALU,also referred to herein as token based pipelining for an intra-ALU tokengating system 2800. The intra-ALU token gating system 2800 comprises aplurality of tokens including a launch token 2802 associated with astart and decode instruction, a register access token 2804 associatedwith reading values from a register file, a jump token 2806 associatedwith a program counter jump, a memory access token 2808 associated withaccessing a memory, an instruction pre-fetch token 2810 associated withfetching the next instruction, an other resources token 2812 associatedwith use of other resources, and a commit token 2814 associated withregister and memory commit.

Designated tokens are used to gate other designated tokens in a givenorder of the pipeline. This means that when a designated token passesthrough an ALU, a second designated token is then allowed to beprocessed and passed by the same ALU in the token ring architecture. Inother words, releasing one token by the ALU becomes a condition toconsume (process) another token in that ALU in that given order.

A particular example of a token-gating relationship is illustrated inFIG. 6. It will be appreciated by one skilled in the art that othertoken-gating relationships may be used. In the illustrated example, thelaunch token (L) 2802 gates the register access token (R) 2804, which inturn gates the jump token (PC token) 2806. The jump token 2806 gates thememory access token (M) 2808, the instruction pre-fetch token (F) 2810,and possibly other resource tokens 2812 that may be used. This meansthat tokens M 2808, F 2810, and other resource tokens 2812 can only beconsumed by the ALU after passing the jump token 2806. These tokens gatethe commit token (W) 2814 to register or memory. The commit token 2814is also referred to herein as a token for writing the instruction. Thecommit token 2814 in turn gates the launch token 2802. The gating signalfrom the gating token (a token in the pipeline) is used as input into aconsumption condition logic of the gated token (the token in the nextorder of the pipeline). For example, the launch token (L) 2802 generatesan active signal to the register access or read token (R) 2804, when thelaunch token (L) 2802 is released to the next ALU. This guarantees thatany ALU would not read the register file until an instruction isactually started by the launch token 2802.

FIG. 7 illustrates token based pipelining for an inter-ALU token passingsystem 2900. The inter-ALU token passing system 2900 comprises a firstALU 2902 and a second ALU 2904. A consumed token signal triggers a pulseto a common resource. For example, the register read token 2804 in thefirst CPU 2902 triggers a pulse to the register file (not shown). Thetoken signal is delayed before it is released to the next ALU (e.g., thesecond ALU 2904) for a period of time such that there is no structuralhazard on this common resource (e.g., the register file) between thefirst ALU 2902 and the second ALU 2904. The tokens not only preservemultiple ALUs from launching and committing (or writing) instructions inthe program counter (PC) order, but also avoid structural hazard amongthe multiple ALUs.

FIG. 8 illustrates a block diagram of an exemplary token ring basedarray architecture 2700. As illustrated, the token ring based arrayarchitecture 2700 comprises a plurality of processing units 2702, atoken signal path or ring 2704 comprising a plurality of tokens, amultiplexor 2706, and a plurality of external resources 2708 sharedbetween the processing units 2702. In the illustrated example, theprocessing units 2702 are identical in design and function to oneanother. In a non-limiting example, the processing units 2702 implementarithmetic and logic units (ALUs). The ALUs 2702 may be asynchronousunits.

The token ring 2704 allows propagation of a token through the ALUs 2702.Token processing logic is provided (not shown) for propagating the tokenfrom one ALU to other ALU amongst the ALUs 2702 along the token ring2704. The token processing logic is configured to propagate the tokenbetween the ALUs 2708 at a propagation rate that is related to atransaction rate of the shared external resource 2708. For example, therate at which the ALU completes a transaction may vary depending on thespecific transaction requested.

Each token in the token ring 2704 is a signal indicator for theavailability of one or more of the external resources 2708. The token issuch that only one ALU amongst the ALUs 2702 can possess it at any giventime. In a specific example of implementation, possession of the tokenby a given ALU enables the given ALU to conduct a transaction with theshared external resource 2708. Conversely, lack of possession of thetoken by the given ALU prevents the given ALU from conducting atransaction with the shared external resource 2708. In this manner, thetoken allows preventing more than one ALU from conducting a transactionwith the external resource 2708 at a given time. After a given ALUconducts a transaction with the shared external resource 2708, or if thegiven ALU does not wish to conduct a transaction with the sharedexternal resource 2708, the ALU releases or “passes” the token to thenext ALU. Serialized in this way, multiple ALUs can share a commonexternal resource. As illustrated, multiple tokens may be required tocontrol access to the shared external resources 2708 via an N-bitselection control signal 2712 and the multiplexor 2706.

FIG. 9 illustrates an exemplary embodiment of a token ring basedparallel processor asynchronous scheduler 3000. As illustrated, amultiple token ring 3010 similar to the token ring 2704 described abovewith respect to FIG. 8 is used to control access of different externalcommon resources 2708 between a first ALU (e.g., ALU 0) 2902, a secondALU (e.g., ALU 1) 2904, etc. In addition, token dependency and gatingsimilar to the intra-token gating system 2800 described above withrespect to FIG. 28 is used to form a pipeline with different stageswithin a given ALU. By using a multiple token ring to control access ofdifferent external common resources and token dependency and gating toform a pipeline with different stages, multiple asynchronous ALUs can becombined as a parallel processor 3030. As a result, natural pipelinestages may be formed unlike a synchronous processor that has fixedperiod pipeline stages.

FIG. 10 illustrates a more detailed view of the token ring basedparallel processor asynchronous scheduler of FIG. 9, where token ringsignal paths of the tokens are illustrated by “dashed” lines, and wheretoken dependence signal paths of the tokens are illustrated by “solid”lines. For example, inter-ALU token passing as described above withrespect to FIG. 7 is illustrated by the launch token 2802 being passedfrom ALU 0 2902 to ALU 1 2904 via token ring signal path 3104. Inaddition, intra-ALU token passing as described above with respect toFIG. 6 is illustrated by launch token dependency signal 3106 from thelaunch token 2802 gating the register access token 2804. The othertokens (e.g., the register access token (R) 2804, the jump token (PCtoken) 2806, etc.) may be similarly passed between the ALUs and withinthe ALUs, respectively.

FIG. 11 illustrates an example communication system 1400 that may beused for implementing the devices and methods disclosed herein. Ingeneral, the system 1400 enables multiple wireless users to transmit andreceive data and other content. The system 1400 may implement one ormore channel access methods, such as code division multiple access(CDMA), time division multiple access (TDMA), frequency divisionmultiple access (FDMA), orthogonal FDMA (OFDMA), or single-carrier FDMA(SC-FDMA).

In this example, the communication system 1400 includes user equipment(UE) 1410 a-1410 c, radio access networks (RANs) 1420 a-1420 b, a corenetwork 1430, a public switched telephone network (PSTN) 1440, theInternet 1450, and other networks 1460. While certain numbers of thesecomponents or elements are shown in FIG. 14, any number of thesecomponents or elements may be included in the system 1400.

The UEs 1410 a-1410 c are configured to operate and/or communicate inthe system 1400. For example, the UEs 1410 a-1410 c are configured totransmit and/or receive wireless signals or wired signals. Each UE 1410a-1410 c represents any suitable end user device and may include suchdevices (or may be referred to) as a user equipment/device (UE),wireless transmit/receive unit (WTRU), mobile station, fixed or mobilesubscriber unit, pager, cellular telephone, personal digital assistant(PDA), smartphone, laptop, computer, touchpad, wireless sensor, orconsumer electronics device.

The RANs 1420 a-1420 b here include base stations 1470 a-1470 b,respectively. Each base station 1470 a-1470 b is configured towirelessly interface with one or more of the UEs 1410 a-1410 c to enableaccess to the core network 1430, the PSTN 1440, the Internet 1450,and/or the other networks 1460. For example, the base stations 1470a-1470 b may include (or be) one or more of several well-known devices,such as a base transceiver station (BTS), a Node-B (NodeB), an evolvedNodeB (eNodeB), a Home NodeB, a Home eNodeB, a site controller, anaccess point (AP), or a wireless router, or a server, router, switch, orother processing entity with a wired or wireless network.

In the embodiment shown in FIG. 11, the base station 1470 a forms partof the RAN 1420 a, which may include other base stations, elements,and/or devices. Also, the base station 1470 b forms part of the RAN 1420b, which may include other base stations, elements, and/or devices. Eachbase station 1470 a-1470 b operates to transmit and/or receive wirelesssignals within a particular geographic region or area, sometimesreferred to as a “cell.” In some embodiments, multiple-inputmultiple-output (MIMO) technology may be employed having multipletransceivers for each cell.

The base stations 1470 a-1470 b communicate with one or more of the UEs1410 a-1410 c over one or more air interfaces 1490 using wirelesscommunication links. The air interfaces 1490 may utilize any suitableradio access technology.

It is contemplated that the system 1400 may use multiple channel accessfunctionality, including such schemes as described above. In particularembodiments, the base stations and UEs implement LTE, LTE-A, and/orLTE-B. Of course, other multiple access schemes and wireless protocolsmay be utilized.

The RANs 1420 a-1420 b are in communication with the core network 1430to provide the UEs 1410 a-1410 c with voice, data, application, Voiceover Internet Protocol (VoIP), or other services. Understandably, theRANs 1420 a-1420 b and/or the core network 1430 may be in direct orindirect communication with one or more other RANs (not shown). The corenetwork 1430 may also serve as a gateway access for other networks (suchas PSTN 1440, Internet 1450, and other networks 1460). In addition, someor all of the UEs 1410 a-1410 c may include functionality forcommunicating with different wireless networks over different wirelesslinks using different wireless technologies and/or protocols.

Although FIG. 11 illustrates one example of a communication system,various changes may be made to FIG. 11. For example, the communicationsystem 1400 could include any number of UEs, base stations, networks, orother components in any suitable configuration, and can further includethe EPC illustrated in any of the figures herein.

FIGS. 12A and 12B illustrate example devices that may implement themethods and teachings according to this disclosure. In particular, FIG.12A illustrates an example UE 1410, and FIG. 12B illustrates an examplebase station 1470. These components could be used in the system 140A orin any other suitable system.

As shown in FIG. 12A, the UE 1410 includes at least one processing unit1500. The processing unit 1500 implements various processing operationsof the UE 1410. For example, the processing unit 1500 could performsignal coding, data processing, power control, input/output processing,or any other functionality enabling the UE 1410 to operate in the system1400. The processing unit 1500 also supports the methods and teachingsdescribed in more detail above. Each processing unit 1500 includes anysuitable processing or computing device configured to perform one ormore operations. Each processing unit 1500 could, for example, include amicroprocessor, microcontroller, digital signal processor, fieldprogrammable gate array, or application specific integrated circuit. Theprocessing unit 1500 may be an asynchronous processor as describedherein.

The UE 1410 also includes at least one transceiver 1502. The transceiver1502 is configured to modulate data or other content for transmission byat least one antenna 1504. The transceiver 1502 is also configured todemodulate data or other content received by the at least one antenna1504. Each transceiver 1502 includes any suitable structure forgenerating signals for wireless transmission and/or processing signalsreceived wirelessly. Each antenna 1504 includes any suitable structurefor transmitting and/or receiving wireless signals. One or multipletransceivers 1502 could be used in the UE 1410, and one or multipleantennas 1504 could be used in the UE 1410. Although shown as a singlefunctional unit, a transceiver 1502 could also be implemented using atleast one transmitter and at least one separate receiver.

The UE 1410 further includes one or more input/output devices 1506. Theinput/output devices 1506 facilitate interaction with a user. Eachinput/output device 1506 includes any suitable structure for providinginformation to or receiving information from a user, such as a speaker,microphone, keypad, keyboard, display, or touch screen.

In addition, the UE 1410 includes at least one memory 1508. The memory1508 stores instructions and data used, generated, or collected by theUE 1410. For example, the memory 1508 could store software or firmwareinstructions executed by the processing unit(s) 1500 and data used toreduce or eliminate interference in incoming signals. Each memory 1508includes any suitable volatile and/or non-volatile storage and retrievaldevice(s). Any suitable type of memory may be used, such as randomaccess memory (RAM), read only memory (ROM), hard disk, optical disc,subscriber identity module (SIM) card, memory stick, secure digital (SD)memory card, and the like.

As shown in FIG. 12B, the base station 1470 includes at least oneprocessing unit 1500, at least one transmitter 1552, at least onereceiver 1554, one or more antennas 1556, one or more network interfaces1560, and at least one memory 1558. The processing unit 1500 implementsvarious processing operations of the base station 1470, such as signalcoding, data processing, power control, input/output processing, or anyother functionality. The processing unit 1500 can also support themethods and teachings described in more detail above. Each processingunit 1500 includes any suitable processing or computing deviceconfigured to perform one or more operations. Each processing unit 1500could, for example, include a microprocessor, microcontroller, digitalsignal processor, field programmable gate array, or application specificintegrated circuit. The processing unit 1500 may be an asynchronousprocessor as described herein.

Each transmitter 1552 includes any suitable structure for generatingsignals for wireless transmission to one or more UEs or other devices.Each receiver 1554 includes any suitable structure for processingsignals received wirelessly from one or more UEs or other devices.Although shown as separate components, at least one transmitter 1552 andat least one receiver 1554 could be combined into a transceiver. Eachantenna 1556 includes any suitable structure for transmitting and/orreceiving wireless signals. While a common antenna 1556 is shown here asbeing coupled to both the transmitter 1552 and the receiver 1554, one ormore antennas 1556 could be coupled to the transmitter(s) 1552, and oneor more separate antennas 1556 could be coupled to the receiver(s) 1554.Each memory 1558 includes any suitable volatile and/or non-volatilestorage and retrieval device(s).

Additional details regarding UEs 1410 and base stations 1470 are knownto those of skill in the art. As such, these details are omitted herefor clarity.

In some embodiments, some or all of the functions or processes of theone or more of the devices are implemented or supported by a computerprogram that is formed from computer readable program code and that isembodied in a computer readable medium. The phrase “computer readableprogram code” includes any type of computer code, including source code,object code, and executable code. The phrase “computer readable medium”includes any type of medium capable of being accessed by a computer,such as read only memory (ROM), random access memory (RAM), a hard diskdrive, a compact disc (CD), a digital video disc (DVD), or any othertype of memory.

It may be advantageous to set forth definitions of certain words andphrases used throughout this patent document. The terms “include” and“comprise,” as well as derivatives thereof, mean inclusion withoutlimitation. The term “or” is inclusive, meaning and/or. The phrases“associated with” and “associated therewith,” as well as derivativesthereof, mean to include, be included within, interconnect with,contain, be contained within, connect to or with, couple to or with, becommunicable with, cooperate with, interleave, juxtapose, be proximateto, be bound to or with, have, have a property of, or the like.

While this disclosure has described certain embodiments and generallyassociated methods, alterations and permutations of these embodimentsand methods will be apparent to those skilled in the art. Accordingly,the above description of example embodiments does not define orconstrain this disclosure. Other changes, substitutions, and alterationsare also possible without departing from the spirit and scope of thisdisclosure, as defined by the following claims.

What is claimed is:
 1. A method of operating a clock-less asynchronousprocessing system comprising a plurality of successive asynchronousprocessing components, the method comprising: providing a first tokensignal path in the plurality of processing components to allowpropagation of a token through the processing components, whereinpossession of the token by one of the processing components enables theprocessing component to conduct a transaction with a resource componentthat is shared among the processing components; and propagating thetoken from one processing component to another processing componentalong the first token signal path.
 2. The method in accordance withclaim 1, wherein propagating the token is performed at a propagationrate that is related to a latency associated with the processingcomponent.
 3. The method in accordance with claim 2, wherein the latencyis variable and is based on an operation to be conducted by theprocessing component.
 4. The method in accordance with claim 1, whereinpropagating the token is performed at a propagation rate that is relatedto a transaction rate associated with the shared resource component. 5.The method as defined in claim 4, wherein the transaction rate isvariable and is based on the transaction to be conducted with the sharedresource component.
 6. The method in accordance with claim 1, whereinlack of possession of the token by the processing component prevents theprocessing component from conducting a transaction with the sharedresource component.
 7. The method in accordance with claim 1, furthercomprising: in response to determining that the processing componentdesires no transaction with the shared resource component, releasing thetoken so that the token is propagated along the token signal path toanother processing component.
 8. The method in accordance with claim 1,further comprising: providing a second token signal path in theplurality of processing components separate and distinct from the firsttoken signal path to allow propagation of a second token through theprocessing components, wherein the first token signal path and thesecond token signal path form a multi-token ring.
 9. The method inaccordance with claim 8, further comprising: providing anintra-processing component gating system, wherein a first designatedtoken of a plurality of tokens is used to gate other designated tokensin a given order.
 10. The method in accordance with claim 9, whereinreleasing the designated token by the processing component becomes acondition to consume another token in the processing component in thegiven order.
 11. The method in accordance with claim 8, furthercomprising: providing an inter-processing component passing system,wherein the first token is delayed from passing from a first processingcomponent to a second processing component to avoid a structural hazard.12. The method in accordance with claim 11, further comprising:providing an intra-processing component gating system, wherein a firstdesignated token of a plurality of tokens is used to gate otherdesignated tokens in a given order; wherein the inter-processingcomponent passing system and the intra-processing component gatingsystem form a pipeline with different stages.
 13. A clock-lessasynchronous processing system comprising: a plurality of successiveasynchronous processing components, each processing component comprisingtoken processing logic configured to receive, hold and pass a token froma given processing component to another processing component; whereinthe token processing logic comprises a token signal path in theplurality of processing components to allow propagation of the tokenthrough the processing components, wherein possession of the token byone of the processing components enables the processing component toconduct a transaction with a resource component that is shared among theprocessing components.
 14. The processing system in accordance withclaim 13, wherein the token processing logic is configured to propagatethe token at a propagation rate that is related to a latency associatedwith the processing component.
 15. The processing system in accordancewith claim 14, wherein the latency is variable and is based on anoperation to be conducted by the processing component.
 16. Theprocessing system in accordance with claim 13, wherein lack ofpossession of the token by the processing component prevents theprocessing component from conducting a transaction with the sharedresource component.
 17. The processing system in accordance with claim13, wherein the token processing circuitry further comprisesintra-processing component gating circuitry, where a first designatedtoken of a plurality of tokens is used to gate other designated tokensin a given order.
 18. The processing system in accordance with claim 17,wherein releasing the first designated token by the processing componentbecomes a condition to consume another token in the processing componentin the given order.
 19. The processing system in accordance with claim13, wherein the token processing circuitry further comprisesinter-processing component passing circuitry, wherein the token isdelayed from passing from a first processing component to a secondprocessing component to avoid a structural hazard.
 20. The processingsystem in accordance with claim 19, wherein the token processingcircuitry further comprises intra-processing component gating circuitry,wherein a first designated token of a plurality of tokens is used togate other designated tokens in a given order; wherein theinter-processing component passing circuitry and the intra-processingcomponent gating circuitry form a pipeline with different stages.